DC bias of a FET device requires setting of gate-source voltage VGS to provide desired drain current ID. For a JFET drain current is restricted by the saturation current IDS. As the FET has such high input impedance that no gate current flows and DC voltage of the gate set by the voltage divider or a fixed battery voltage is not affected or loaded by FET.
Fixed DC bias is obtained by using a battery VQG. This battery ensures that the gate is negative always with respect to source and no current flows through the resistor RG and gate terminal which is IG =0. The battery gives a voltage VGS to bias the N channel JFET, but no resulting current is drawn from battery VGG. Resistor RG is included to allow any AC signal applied through the capacitor C to develop across RG. While any AC signal will develop across RG, the DC voltage drop across RG is equal to IG RG that is 0 volt.
The gate source voltage VGS is then
VGS = - vG - vs = - vGG - 0 = - VGG
The drain source current ID is fixed by the gate-source voltage as determined by the equation.
This current causes a voltage drop across drain resistor RD and can be given as VRD = IDRD and the output voltage
Vout = VDD - ID RD
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