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Write a Verilog code for synchronous and asynchronous reset?
Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg:
always @ (posedge clk )
begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity list.
Eg
Always @(posedge clock or posedge reset)
begin
if (reset)
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dqueue
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First we must go to bios and should check boot sequence,local add statusOr we should check RAM & check h.d.d cable. check cd writer for cd or dvd
UDP (User Diagram Protocol) is? It is both Connectionless and Message Oriented.
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