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Write a Verilog code for synchronous and asynchronous reset?
Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg:
always @ (posedge clk )
begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity list.
Eg
Always @(posedge clock or posedge reset)
begin
if (reset)
We can modify these objects by saving into image
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give sample prepaired software?
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Nested Macro calls are expanded using the? Ans. By using the LIFO (Last in First out) Nested Macro calls are expanded.
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