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Why a function should have at least one input?
There is no strong reason for this in verilog. I think this restriction isn't removed fin SystemVerilog. Some requirements where inputs are taken from global signal,those functions Don't need any input. A work around is to use a dummy input.
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Whenever we compile with -g option, it will make a symbol table, and according that table for every function and line it will call ptrace.
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what is document works packages?
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function nor gates W=A,B,C,D=~(AB)*~(CD)
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