What is the difference between in two lines of verilog code, Computer Engineering

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What is the difference between the following two lines of Verilog code?

#5 a = b; a = #5 b;

#5 a = b; Wait five time units before doing the action for "a = b;". Value assigned to a will be the value of b 5 time units hence.

a = #5 b; Value of b is calculated and stored in an internal temp register. After five time units, assign this stored value to a.

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