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a) Give eight properties for each of static RAM (SRAM) and DRAM (dynamic RAM) and provide the low-level structure of each type of memory.
b) Assume a system with 16 Megabytes of main memory and a microprocessor that has an on-chip 256 kilobyte 8-way set-associative cache. Consider that each cache line has a size of 32 bytes.
(i) Show a block diagram of this cache showing its organization and how the different address fields are used to evaluate a cache hit/miss.
(ii) Where in the cache will the byte from memory location DECADE16 be mapped?
Expain the working of associative memory
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how to stud for subject microprocessor
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Static RAM: No refreshing, 6 to 8 MOS transistors are needed to form one memory cell, Information stored as voltage level in a flip flop. Dynamic RAM: Refreshed periodically, 3
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