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a) Give eight properties for each of static RAM (SRAM) and DRAM (dynamic RAM) and provide the low-level structure of each type of memory.
b) Assume a system with 16 Megabytes of main memory and a microprocessor that has an on-chip 256 kilobyte 8-way set-associative cache. Consider that each cache line has a size of 32 bytes.
(i) Show a block diagram of this cache showing its organization and how the different address fields are used to evaluate a cache hit/miss.
(ii) Where in the cache will the byte from memory location DECADE16 be mapped?
Q. Show Error detection mechanism? Error detection mechanism can be described as below: Figure: Error detection and correction
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State the optimal route of node Consider the node i which has path length K+1, with the directly preceding node on the path being j. The distance to node i is w(j, i) plus the
The CCITT standard bandwidth for speech is: (A) 20000 Hz (B) 15000 Hz (C) 7000 Hz (D) 3400 Hz Ans:
Compare a decoder and a demultiplexer with suitable block diagrams. Ans. Demultiplexer has similar circuit as decoder but here e is obtained as the particular input line, the
What is LoadRunner
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what is picket fence problem?
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