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a) Give eight properties for each of static RAM (SRAM) and DRAM (dynamic RAM) and provide the low-level structure of each type of memory.
b) Assume a system with 16 Megabytes of main memory and a microprocessor that has an on-chip 256 kilobyte 8-way set-associative cache. Consider that each cache line has a size of 32 bytes.
(i) Show a block diagram of this cache showing its organization and how the different address fields are used to evaluate a cache hit/miss.
(ii) Where in the cache will the byte from memory location DECADE16 be mapped?
Q. Explain about Karnaugh Maps? Karnaugh maps are a suitable way of expressing and simplifying Boolean function of 2 to 6 variables. The stepwise process for Karnaugh map is.
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#questifind core radius for single mode operation at 850nm in SI fibre with n1=1.480 & n2=1.47 what is NAon..
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