Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. What is Memory Interleaving?
In this scheme main memory is splitted in 'n' equal-size modules and CPU has separate Memory Base register and Memory Address Register for every memory module. Additionally CPU has 'n' instruction register and a memory access system. When a program is loaded in main memory its successive instructions are stored in successive memory modules. For illustration if n=4 and four memory modules are M1, M2, M3, and M4 then 1st instruction would be stored in M1, 2nd in M2, 3rd in M3, 4th in M4, 5th in M1, 6th in M2 and so on. Now at the time of execution of program when processor issues a memory fetch command then memory access system creates n consecutive memory addresses and places them in Memory Address Register in right order. A memory read command interprets all 'n' memory modules concurrently and retrieves 'n' consecutive instructions as well as loads them in the 'n' instruction registers. So every fetch for a new instruction results in loading of 'n' consecutive instructions in 'n' instruction registers of CPU. Because instructions are generally executed in sequence in which they were written, availability of N successive instructions in CPU avoids memory access after every instruction execution and total execution time speeds up. Apparently fetch successive instructions aren't useful when a branch instruction is encountered at the time of course of execution. This is because they need new set of 'n' successive instructions, overwriting previously stored instructions that were loaded however some of which weren't executed. The method is very efficient in minimising memory-processor speed mismatch since branch instructions don't take place often in a program.
Figure below explains memory interleaving architecture. The Figure shows a 4- way (n=4) interleaved memory system.
Figure: A 4-way Interleaved Memory
Q. What is Memory Address Register? Memory Address Register (MAR): It specifies address of memory location from that data or instruction is to be accessed (read operation) or t
What is major difference between the Historic Unix and the new BSD release of Unix System V in terms of Memory Management? Historic Unix uses Swapping - Whole process is tran
Java bean is a reusable component, where as the servlet is the java program which extends the server capability.
Example of circuit switching and S&F (Stored and Forward) switching is (A) Telephone and Post of Telegraph (B) Video Signal Post or Telegraph (C) Digital Signal P
Which device consume minimum power ? Ans. Minimum power consume by CMOS as in its one p-MOS and one n-MOS transistors are connected in complimentary mode, so one device is ON a
A class that has no functionality of its own is an Adaptor class in C++. Its member functions hide the use of a third party software component or an object with the non-compatible
Illustrate the term EDI Trading Patterns? EDI Trading Patterns are illustrated below: a. Hubs and Spokes: Several of the prime movers into the adoption of Electronic Da
Rational Robot is a whole set of components for automating the testing of Microsoft Windows client/server and Internet applications. The major component of Robot lets you start
The most common type of non-volatile memory is the ROM device. This device is read only and the data is masked into the chip during manufacture. Variations of the ROM are one off p
Explain that the lost acknowledgement does not necessarily enforce retransmission of the packet . To guarantee reliable transfer, protocols utilize positive acknowledgement al
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd