Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. What is Memory Interleaving?
In this scheme main memory is splitted in 'n' equal-size modules and CPU has separate Memory Base register and Memory Address Register for every memory module. Additionally CPU has 'n' instruction register and a memory access system. When a program is loaded in main memory its successive instructions are stored in successive memory modules. For illustration if n=4 and four memory modules are M1, M2, M3, and M4 then 1st instruction would be stored in M1, 2nd in M2, 3rd in M3, 4th in M4, 5th in M1, 6th in M2 and so on. Now at the time of execution of program when processor issues a memory fetch command then memory access system creates n consecutive memory addresses and places them in Memory Address Register in right order. A memory read command interprets all 'n' memory modules concurrently and retrieves 'n' consecutive instructions as well as loads them in the 'n' instruction registers. So every fetch for a new instruction results in loading of 'n' consecutive instructions in 'n' instruction registers of CPU. Because instructions are generally executed in sequence in which they were written, availability of N successive instructions in CPU avoids memory access after every instruction execution and total execution time speeds up. Apparently fetch successive instructions aren't useful when a branch instruction is encountered at the time of course of execution. This is because they need new set of 'n' successive instructions, overwriting previously stored instructions that were loaded however some of which weren't executed. The method is very efficient in minimising memory-processor speed mismatch since branch instructions don't take place often in a program.
Figure below explains memory interleaving architecture. The Figure shows a 4- way (n=4) interleaved memory system.
Figure: A 4-way Interleaved Memory
advantages of lfu
Charles Babbage 'The grandfather of modern computer' had designed two computers: The Difference Engine: It was based on mathematical principle of finite differences and was us
Potential of Parallelism Problems in the actual world differ in respect of the degree of natural parallelism inherent in the personal problem domain. Some problems may be simpl
Discuss the functioning of different network access equipments. The E1 multiplexers MX2000 and MX2411 and E1/T1 MX200 are giving multi interface user access to network PDH or S
What is Hamiltonian path? A Hamiltonian path in a directed graph G is a directed path that goes through every node exactly once. We consider a special case of this problem whe
Features of MPI-1 Binding for FORTRAN and C Collective communication Communication domains and Process groups Point-to-point communication Virtual process
Q. Define Organizing? Grouping of related activities together, Identification of required activities and forming departments and coordinating various departments with the estab
THE NEED OF PARALLEL COMPUTATION With the growth of computer science, computational pace of the processors has also increased many a times. Though, there are definite constr
Summary of Tasks Task Summary attempts to show amount of duration every task has spent starting from beginning of task until its completion on any processor as displayed in Fi
A) What does this file have? Where was the information in this file acquired from? What is the information in this file used for? B) What is the range for popular ports? What i
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd