Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. What is Memory Interleaving?
In this scheme main memory is splitted in 'n' equal-size modules and CPU has separate Memory Base register and Memory Address Register for every memory module. Additionally CPU has 'n' instruction register and a memory access system. When a program is loaded in main memory its successive instructions are stored in successive memory modules. For illustration if n=4 and four memory modules are M1, M2, M3, and M4 then 1st instruction would be stored in M1, 2nd in M2, 3rd in M3, 4th in M4, 5th in M1, 6th in M2 and so on. Now at the time of execution of program when processor issues a memory fetch command then memory access system creates n consecutive memory addresses and places them in Memory Address Register in right order. A memory read command interprets all 'n' memory modules concurrently and retrieves 'n' consecutive instructions as well as loads them in the 'n' instruction registers. So every fetch for a new instruction results in loading of 'n' consecutive instructions in 'n' instruction registers of CPU. Because instructions are generally executed in sequence in which they were written, availability of N successive instructions in CPU avoids memory access after every instruction execution and total execution time speeds up. Apparently fetch successive instructions aren't useful when a branch instruction is encountered at the time of course of execution. This is because they need new set of 'n' successive instructions, overwriting previously stored instructions that were loaded however some of which weren't executed. The method is very efficient in minimising memory-processor speed mismatch since branch instructions don't take place often in a program.
Figure below explains memory interleaving architecture. The Figure shows a 4- way (n=4) interleaved memory system.
Figure: A 4-way Interleaved Memory
Q. Describe the Errors? Errors Two probabletypes of errors may take place in assembly programs: a. Programming errors: They are familiar errors you may encounter in
Virtual Manufacturing System Virtual manufacturing system or VMS is a synthetic, integrated manufacturing environment, developed by using information technology tools, exercise
Q. Explain about Instruction Register and Flags? The Instruction Register: It comprises the operation code (opcode) and addressing mode bits of the instruction. It assists in
An amplifier has an input resistance of 600 ohms and a resistive load of 75 ohms. When it has an rms input voltage of 100 mV, the rms output current is 20mA. Find the gain in dB.
Trunks are the lines that run between (A) subscribers and exchange (B) switching system and power plant (C) Local Area Network (D) switching syste
In a particular exchange during busy hour 1200 calls were offered to a group of trunks, during this time 6 calls were lost. The average call duration being 3 minutes Calculate
Your JDBC code may throw the following exception: "The coordinator has rolled back the transaction.No further JDBC access is permitted within this transaction." The WebLogic
TARGET = "_self" "_self" puts the new document in the same window and frame as current document. "_self" works the same as if you hadn't used TARGET at all.
Define the concept of Typing of object oriented analysis Typing enforces object class such that objects of different classes cannot be interchanged. Or we can say that, class
Traffic Intensity can be measured in (A) Erlangs (B) CCS (C) CM (D) All of the above Ans:
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd