Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. What is Memory Interleaving?
In this scheme main memory is splitted in 'n' equal-size modules and CPU has separate Memory Base register and Memory Address Register for every memory module. Additionally CPU has 'n' instruction register and a memory access system. When a program is loaded in main memory its successive instructions are stored in successive memory modules. For illustration if n=4 and four memory modules are M1, M2, M3, and M4 then 1st instruction would be stored in M1, 2nd in M2, 3rd in M3, 4th in M4, 5th in M1, 6th in M2 and so on. Now at the time of execution of program when processor issues a memory fetch command then memory access system creates n consecutive memory addresses and places them in Memory Address Register in right order. A memory read command interprets all 'n' memory modules concurrently and retrieves 'n' consecutive instructions as well as loads them in the 'n' instruction registers. So every fetch for a new instruction results in loading of 'n' consecutive instructions in 'n' instruction registers of CPU. Because instructions are generally executed in sequence in which they were written, availability of N successive instructions in CPU avoids memory access after every instruction execution and total execution time speeds up. Apparently fetch successive instructions aren't useful when a branch instruction is encountered at the time of course of execution. This is because they need new set of 'n' successive instructions, overwriting previously stored instructions that were loaded however some of which weren't executed. The method is very efficient in minimising memory-processor speed mismatch since branch instructions don't take place often in a program.
Figure below explains memory interleaving architecture. The Figure shows a 4- way (n=4) interleaved memory system.
Figure: A 4-way Interleaved Memory
Q. Explain about PARAM Super computer? PARAM is a high-performance, industry standard and scalable computer. It has developed from concepts of distributes scalable computers ma
Explain the Optimization of data access paths Optimization is a very significant aspect of any design. The designer must do the followings for optimization: i) Add redundan
Differentiate between protected and real modes of an Intel microprocessor Operation of Real mode interrupt: When microprocessor completes executing the current instruction, it
The declaration tells the compiler that at some later point we plan to show the definition of this declaration. E.g.: void stars () //function declaration The definition con
Explain in detail companding. Companding: It is the process of compressing and expanding. This includes compressing the signal at the transmitter and expanding this at the re
A disk drive with removable disks is known as removable drive. A removable disk can be replaced by other similar disk on same or different computer so providing huge data storage w
One of these objectives is related to costs. By going e-commerce, consumers will be able to submit their purchase requests to the sellers without paying a visit to their place. Thi
Server can interact with more than one client with using threading concepts there are java threads which are allocated to each client when he logs in to server, the thread handles
Concept of Multithreading: This problem rises in design of large scale multiprocessors like MPP. So a solution for optimizing this latency must be acquired at. The idea of Mul
project
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd