Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. What is Memory Interleaving?
In this scheme main memory is splitted in 'n' equal-size modules and CPU has separate Memory Base register and Memory Address Register for every memory module. Additionally CPU has 'n' instruction register and a memory access system. When a program is loaded in main memory its successive instructions are stored in successive memory modules. For illustration if n=4 and four memory modules are M1, M2, M3, and M4 then 1st instruction would be stored in M1, 2nd in M2, 3rd in M3, 4th in M4, 5th in M1, 6th in M2 and so on. Now at the time of execution of program when processor issues a memory fetch command then memory access system creates n consecutive memory addresses and places them in Memory Address Register in right order. A memory read command interprets all 'n' memory modules concurrently and retrieves 'n' consecutive instructions as well as loads them in the 'n' instruction registers. So every fetch for a new instruction results in loading of 'n' consecutive instructions in 'n' instruction registers of CPU. Because instructions are generally executed in sequence in which they were written, availability of N successive instructions in CPU avoids memory access after every instruction execution and total execution time speeds up. Apparently fetch successive instructions aren't useful when a branch instruction is encountered at the time of course of execution. This is because they need new set of 'n' successive instructions, overwriting previously stored instructions that were loaded however some of which weren't executed. The method is very efficient in minimising memory-processor speed mismatch since branch instructions don't take place often in a program.
Figure below explains memory interleaving architecture. The Figure shows a 4- way (n=4) interleaved memory system.
Figure: A 4-way Interleaved Memory
Q. Find the average of two values? Find the average of two values which are stored in ; Memory locations named FIRST and SECOND ; And puts result in memory location AVG
Q. RISC Performance using optimizing compilers? Performance using optimizing compilers: As instructions are simple compilers can be developed for efficient code organization a
plz expalain interfacing of 8259 with 8085 step wise
Stack unwinding in C++ is a process during exception handling when the destructor is known for all local objects the place where the exception was thrown and where it is caught.
A Scrollbar is a Component, but not a Container while Scrollpane is a Container and handles its own events and do its own scrolling.
This comes at the complication time, If we give the LOGO option to the compiler, it take a bitmap file (i.e., ) as logo previous to loading the Application.
Q. Explain Program Source Code? Program Source Code Every assembly language statement appears as: {identifier} Keyword {{parameter},} {;comment}. Element of a
Heuristic Search Strategies: Generally speaking that, a heuristic search is one which have uses a rule of thumb to improve an agent's performance in solving the problems via s
What are transmission bridges? A usual transmission bridge is demonstrated in figure. The series capacitance and the shunt inductances of the two relays give a high-pass filte
Q. In PRAM model steps required for executing an algorithm? Subsequent steps are performed by a PRAM model whenever executing an algorithm: i) Read phase: First the N proc
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd