Q. What is Memory Interleaving?

In this scheme main memory is splitted in 'n' equal-size modules and CPU has separate Memory Base register and Memory Address Register for every memory module. Additionally CPU has 'n' instruction register and a memory access system.  When a program is loaded in main memory its successive instructions are stored in successive memory modules. For illustration if n=4 and four memory modules are M₁, M₂, M₃, and M₄ then 1^st instruction would be stored in M₁, 2^nd in M₂, 3^rd in M₃, 4^th in M₄, 5^th in M₁, 6^th in M₂ and so on.  Now at the time of execution of program when processor issues a memory fetch command then memory access system creates n consecutive memory addresses and places them in Memory Address Register in right order. A memory read command interprets all 'n' memory modules concurrently and retrieves 'n' consecutive instructions as well as loads them in the 'n' instruction registers. So every fetch for a new instruction results in loading of 'n' consecutive instructions in 'n' instruction registers of CPU. Because instructions are generally executed in sequence in which they were written, availability of N successive instructions in CPU avoids memory access after every instruction execution and total execution time speeds up. Apparently fetch successive instructions aren't useful when a branch instruction is encountered at the time of course of execution. This is because they need new set of 'n' successive instructions, overwriting previously stored instructions that were loaded however some of which weren't executed. The method is very efficient in minimising memory-processor speed mismatch since branch instructions don't take place often in a program.

Figure below explains memory interleaving architecture. The Figure shows a 4- way (n=4) interleaved memory system.

Figure: A 4-way Interleaved Memory