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Clk gets its value after 1 time unit, reset after 10 time units, enable after 5 time units, data after 3 time units. All the statements are executed in parallel.
Simulator Output
0 clk=x reset=x enable=x data=x
1 clk=0 reset=x enable=x data=x
3 clk=0 reset=x enable=x data=0
5 clk=0 reset=x enable=0 data=0
10 clk=0 reset=0 enable=0 data=0
tCAS is the number of clock cycles required to access a particular column of data in SDRAM. CAS latency is the column address strobe time, sometimes referred to as tCL.
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