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What is FIFO?
FIFO is used as buffering element or queuing element into the system that is by common sense, is needed only while you slow at reading than the write operation. Therefore size of the FIFO fundamentally implies the amount of data needed to buffer that depends upon data rate at that data is written and the data rate at that data is read. Data rate varies statistically into the system majorly depending onto the load in the system. Therefore to acquire safer FIFO size we require considering the worst case scenario for the data transfer across the FIFO under concerning. For worst scenario case, difference between the data rate between write and read must be maximised. Therefore, for write operation maximum data rate must be considered and for read operation minimum data rate must be considered. Therefore in the question itself, data rate of read operation is specified through the number of idle cycles and for write operation, maximum data rate must be considered along with no idle cycle.
Therefore for write operation, we require to know Data rate = Number of data * rate of clock. There writing side is the source and reading side turns into sinking, data rate of reading side depends onto the writing side data rate and its own reading rate that is Frd/Idle_cycle_rd. In order to identify the data rate of write operation, we require knowing Number of data into a Burst that we have assumed to be B. Therefore following up along with the equation as described below as: Fifo size = Size to be buffered that is implies B - B * Frd / (Fwr* Idle_cycle_rd _rd ).
Now we have not considered the synchronizing latency when Write and Read clocks are Asynchronous. Superior the Synchronizing latency, higher the FIFO size need to buffer more additional data written.
shorte note on hardware description language
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