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Q. What is Block size of cache memory?
Block Size: Block size means unit of data (few memory words) exchanged between main and cache memory. As block size increases from very small to larger size then hit ratio (fraction of times which referenced data/instruction is found in cache) will at first increase due to the principle of locality since more and more useful words are brought into cache. But hit ratio will begin to reduce as block size further increases since probability of using newly fetched words becomes less than probability of reusing words which should be moved out of cache to make room for new block. Relying on this fact block size is rightfully chosen to maximise hit ratio.
Define SR Flip Flop - SR latch with NOR Gate? The SR Flip flop neither is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates. SR
Q. Show Error detection mechanism? Error detection mechanism can be described as below: Figure: Error detection and correction
Explain Flash devices It is possible to read the contents of a one cell, but it is only possible to write an whole block of cells Greater density which leads to superior cap
Which objects are independent transport objects? Domains, Data elements, Tables, Technical settings for tables, Secondary indexes for transparent tables, Structures, Views, Ma
Q. Explain about truth table and logic diagram? A Boolean function can be realized in a logic circuit employing the basic gates: - AND, OR & NOT. Concern here for illustration
How is the command Suppress-Dialog useful? Suppressing whole screens is possible using this command. This command permits us to perform screen processing "in the background".
Question: a Describe the following terms with reference to video editing: 1. Video frame rate 2. Pixel aspect ratio 3. Frame size 4. Temporal compression 5. Spatial comp
The term 'page traffic' describes? Ans. Page Traffic describes the movement of pages in and out of memory.
ISDN handles data pertaining to? ISDN handles data pertaining to all digital services.
Generally the Instruction Set Architecture (ISA) of a processor can be distinguished using five categories: Operand Storage in the CPU - Where are the operands kept other t
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