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Illustrates about Metal Fix.
A Metal Fix implies that only the upper metal interconnects layers are influenced. Connections may be made or broken, but new cells may not be added. A Sewing Kit is an implication of adding a new gate in the design whereas only influencing the metal layers. Sewing Kits are classically added in the initial design either at the RTL level or throughout synthesis trhoguh the customer and are part of the netlist. Usually a Metal Fix influences only the top layers of the wafers and does not influences the "base" layers.
Returns the information about tasks running int info = pvm_tasks( int where, int *ntask, struct pvmtaskinfo **taskp ) struct pvmtaskinfo { int ti_tid; int ti_pt
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