What does formal verification mean, Computer Engineering

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What does formal verification mean?

Formal verification uses Mathematical techniques by proving the design by assertions or properties. Correctness of the design can be achieved by assertions without the need for simulations. The methods of formal verification are

1. Equivalence checking In this process of checking the designs are compared based on mathematical equations and compared whether they are equal or not .

Original RTL vs Modified RTL

- RTL vs Netlist

- Golden Netlist vs Modified/Edited Netlist

- Synthesis Netlist vs Place and route Netlist

 


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