What are advantages and drawbacks of flip-flop?

Usually area of a Flip-flop for features in more than a latch.

Power consumption is normally higher, because of the area and free running clock.

Additional control needed to save power.

As the clock boundaries are rigid, the service of time barrowing or cycle stealing doesn’t exist along with FF’s. The negative slack can’t be propagated to the timing of the subsequent stage pipeline and therefore should execute within a clock cycle.

Clock tree synthesis is less tedious into FF based designs. As the stimulus requirements to be stable before the setup time of the clock, the vector generation is comparatively easier.

Because of rigid timing boundaries, the slowest path pretty much chooses the operating frequency.

The time budgeting is clearer and describing the interfaces is simple.