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VLIW instruction word is compacted to have floating-point addition, one branch, floating point multiply, and one integer arithmetic and load/store operation as displayed in Figure below.
Figure: VLIW instruction word
A VLIW processor to maintain the above instruction word should have the functional elements as displayed in Figure below. All the functional units have been integrated according to VLIW instruction word. All the units in the processor have one common large register file.
Figure: VLIW Processor
Concurrencies in instructions and data movement must be totally specified at compile time however scheduling of branch instructions at compile time is very hard. To handle branch instructions trace scheduling is accepted. Trace scheduling is derived from the prediction of branch decisions with a little reliability at compile time. Prediction is derived from some heuristics hints given by programmer or using profiles of a number of previous program executions.
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One Erlang is equal to (A) 3600 CCS (B) 36 CCS (C) 60 CCS (D) 24 CCS Ans: One Erlang is equivalent to 3600 CCS.
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The number of control lines for 16 to 1 multiplexer is ? Ans. We have 16 = 2 4 , 4 Select lines are needed.
How many 128 × 8 RAM chips are required to provide a memory capacity of 2048 bytes. Ans. Available here RAM chips = 128 x 8 Required the memory capacity = 2048 x 8 No. of chip
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