Types of bus - computer architecture, Computer Engineering

Assignment Help:

Types of Bus:

Synchronous Bus

  • All devices gain timing information from a common clock line.
  • Each of these intervals constitutes a bus cycle at the time duration which 1 data transfer can take place.

1434_Types of Bus.png

Synchronous Bus Input Transfer

394_Types of Bus1.png

Asynchronous Bus

o   The common clock is replaced by 2 timing control lines Slave- ready and Master-ready.

o   Data transfers on the bus are based on the utilization of a handshake among the master and the salve.

2223_Types of Bus2.png

 


Related Discussions:- Types of bus - computer architecture

Write a verilog code to swap contents of two registers, Write  a  verilog  ...

Write  a  verilog  code  to  swap  contents  of  two registers  with  and without  a  temporary register? With temp reg : always @ (posedge clock) begin temp=b; b

What are two methods of modifying sap standard tables, What are two methods...

What are two methods of modifying SAP standard tables? Append Structures and Customizing Includes.

What is read-only-memory, Q. What is Read-only-Memory? Read only memory...

Q. What is Read-only-Memory? Read only memory is an illustration of a Programmable Logic Device (PLD) it implies that binary information which is stored within a PLD is specifi

Why does ftp use two standard ports, Why does FTP use two standard ports wh...

Why does FTP use two standard ports whereas other protocols, in general use only one port? Justify. File transfer protocol uses a control connection just to send commands and r

State in brief about third generation electronic computers, Third Generatio...

Third Generation (1963-1972) The third generation introduced huge gains in computational power. Innovations in this time include use of integrated circuits or ICs (semiconducto

Features of read-only memory, Q. Features of read-only memory? ROMs are...

Q. Features of read-only memory? ROMs are memories on which it's not possible to write data when they are on-line to computer. They can only be read. This is reason why it is k

What is an interpreted languages, What is an interpreted languages In ...

What is an interpreted languages In interpreted languages, the instructions are implemented immediately after parsing. Both tasks are done by the interpreter. The code is sav

Address phase - computer architecture, Address phase: A PCI bus transa...

Address phase: A PCI bus transaction starts having an address phase. The initiator,  after seeing that it has GNT# and the bus is inactive, drives the target address onto the

Communications between r/3 and external applications, What is the means of ...

What is the means of communications between R/3 and external applications? The means of communication among R/2,R/3 and external applications is by the CPI-C handler or SAP Gat

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd