Successive approximation ADC

One method of addressing digital ramp ADC's shortcomings is so-called successive approximation ADC. Only change in this design is a very special counter circuit called a successive-approximation register. Rather than counting up in binary sequence, this register counts by trying all values of bits starting with most significant bit and finishing at least-significant bit. During the count process, register monitors the comparator's output to see if binary count is greater than or less than analog signal input, adjusting bit values accordingly. The way the register counts is identical to 'trial-and-fit' method of decimal-to-binary conversion whereby different values of bits are tried from Most Significant Bit to Least Significant Bit to get a binary number which equals original decimal number. The benefit to this counting strategy is much faster results: DAC output converges on analog signal input in much larger steps than with 0-to-full count sequence of a regular counter. 

Without demonstrating inner workings of successive-approximation register (SAR), circuit looks like this: 

Fig: Successive Approximation ADC Circuit

 It must be noted that SAR is normally capable of outputting the binary number in serial (one bit at a time) format hence eliminating the need for a shift register. Plotted over time, operation of a successive-approximation ADC looks like this:

Fig: Successive Approximation ADC Circuit Input and output Waveforms