Q. Show Two Way Pipelined Timing?

Figure below demonstrates a simple pipelining scheme in which F and E stages of two different instructions are performed concurrently. This scheme increases the execution rate of sequential scheme.

Figure: Two Way Pipelined Timing

Please note that pipeline above isn't running at its full capacity. This is ought to the following problems:

• We are presuming a single port memory so only one memory access is permitted at aninstance. SoData and Fetch transfer operations can't take place at the same instance. So you may notice blank in time slot 3, 5 etc.
• Last instruction is an unconditional jump. Please note that after this instruction subsequent instruction of calling program will be executed. Though not visible in this illustration a branch instruction interrupts the sequential flow of instruction execution. So causing inefficiencies in pipelined execution.

This pipeline can simply be improved by allowing two memory accesses at a time.  

So modified pipeline will be:

Pipeline may suffer due to data dependencies and branch instructions penalties. A good pipeline has equivalent phases.

Figure: Three-way Pipelining Timing