Register transfer - computer architecture:

Register transfer: The output and input gates for register Ri are controlled by the signals Riout and Riin respectively.

• Therefore, when Riin is set to 1, the data available on the common bus is loaded into Ri.
• in similar manner, when Riout is set to 1, the contents of register Ri are placed on the bus.
• Whereas Riout is equal to 0, the bus may be used for transferring data from other registers.

Now consider data transfer among2 registers. For instance, to transfer the contents of register R1 toR4, the following actions are required:

Enable the output gate of R1 register by setting R1out to 1. It places the contents of R1 on the CPU bus.

• Enable the input gate of R4 register by setting R4in to 1. It loads data from the CPU bus into register R4.
• This data transfer may be represented representatively as R1out, R4in