Register data type as sequential element, Computer Engineering

Assignment Help:

Reg data type as Sequential element

module reg_seq_example( clk, reset, d, q);

input clk, reset, d;

output q;

reg q;

wire clk, reset, d;

always @ (posedge clk or posedge reset)

if (reset) begin

q <= 1'b0;

end else begin

q <= d;

end

endmodule

There is a difference in the process of assigning to reg when modeling combinational logic: in this logic we use blocking assignments when modeling sequential logic we use nonblocking ones.

 


Related Discussions:- Register data type as sequential element

Design combinational-sequential electronic logic gate, Combinational/Sequen...

Combinational/Sequential Logic design with Integrated Circuits (Dual in line package) Car wash concept with the following steps in a Combinational Logic Diagram: 1.    Start

Perfect induction, Any identity or equality in Boolean algebra, suchas de M...

Any identity or equality in Boolean algebra, suchas de Morgan's Theorem can be proved usingthe method of perfect induction. 1. All combinations of variables are written down.

Describe the architecture of electronic data exchange, Describe the Electro...

Describe the Electronic Data Exchange (EDI) architecture in brief. Electronic Data Interchange (EDI) may be generally easy to understand as the replacement of paper-based purch

How many octets does smallest possible ipv6 datagram contain, How many Octe...

How many Octets does the smallest possible IPV6 datagram contain? The maximum size of an Ipv6 datagram is 65575 bytes, with the 0 bytes Ipv6 header. Ipv6 also describe a minim

Which language is a platform free language, Which language  is a platform ...

Which language  is a platform free language Java language

Convert the following from octal to binary, Q. Convert the following from o...

Q. Convert the following from octal to binary, decimal, hexadecimal and BCD. a) 7.7 b) 4037 c) 23.34

What is pli, What is PLI Programming  Language  Interface  (PLI)  of  V...

What is PLI Programming  Language  Interface  (PLI)  of  Verilog  HDL  is  a  mechanism  to  interface  Verilog programs  with  programs  written  in  C  language.  It also pro

Slot machine, A special Slot Machine is introduced in a new casino; this ma...

A special Slot Machine is introduced in a new casino; this machine has a digital interface of a 3X3 grid. An interface button named as SPIN for making the machine spin. There are f

Define the time when a block of data is ready to be read, The total time to...

The total time to prepare a disk drive mechanism for a block of data to be read from is its ? Ans. latency plus seek time is the total time to prepare a disk drive mechanism fo

How does tcp achieve reliability, How does TCP achieve reliability? One...

How does TCP achieve reliability? One of the most significant technologies is retransmission. While TCP stands data the sender compensates for packet loss through implementing

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd