Register data type as sequential element, Computer Engineering

Assignment Help:

Reg data type as Sequential element

module reg_seq_example( clk, reset, d, q);

input clk, reset, d;

output q;

reg q;

wire clk, reset, d;

always @ (posedge clk or posedge reset)

if (reset) begin

q <= 1'b0;

end else begin

q <= d;

end

endmodule

There is a difference in the process of assigning to reg when modeling combinational logic: in this logic we use blocking assignments when modeling sequential logic we use nonblocking ones.

 


Related Discussions:- Register data type as sequential element

What is over-clocking, Overclocking is the process of making a computer or ...

Overclocking is the process of making a computer or component operate faster than the clock frequency particular by the manufacturer by modifying system parameters. One of the most

What is time multiplexed space switching, What is time multiplexed space sw...

What is time multiplexed space switching? Explain w ith a neat diagram. Time division switches, an inlet or an outlet corresponded to a particular subscriber line with one s

What is a packet switching, End systems are connected together by communica...

End systems are connected together by communication links. There are various types of communication links, which are made of numerous types of physical media, comprising twisted pa

What are the data types of the external layer, What are the Data types of t...

What are the Data types of the external layer? The Data types of the external layer are :- ACCP, Char, CLNT, CUKY, CURR, DATS, DESC, FLTP, INT1, INT2, INT4, LANG, LCHR, L

How are the function code handles in flow logic, How are the function code ...

How are the function code handles in Flow Logic? When the User selects a function in a transaction, the system copies the function code into a           specially   designated

Explain vector processing with pipelining, Vector Processing with Pipelinin...

Vector Processing with Pipelining Because in vector processing vector instructions execute the similar computation on various data operands repeatedly, vector processing is the

Mips assembly language equivalents , MIPS' native assembly code only has tw...

MIPS' native assembly code only has two branch instructions, beq and bne, and only one comparison instruction, slt. Using just these three instructions (along with the ori instruct

What do you mean by memory mapped i/o, What do you mean by memory mapped I/...

What do you mean by memory mapped I/O? In Memory mapped I/O, there is no particular input or output instructions. The CPU can manipulate I/O data residing in interface register

Illustration of an instruction cycle, Q. Illustration of an instruction cyc...

Q. Illustration of an instruction cycle? Instruction cycle displayed in given figure comprises subsequent stages: First address of the subsequent instruction is calculat

What is synchronous transmission, What is synchronous transmission? In ...

What is synchronous transmission? In synchronous transmission the two units share a common frequency and bits are transmitted continuously at the rate dictated  by clock pulses

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd