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Reg data type as Sequential element
module reg_seq_example( clk, reset, d, q);
input clk, reset, d;
output q;
reg q;
wire clk, reset, d;
always @ (posedge clk or posedge reset)
if (reset) begin
q <= 1'b0;
end else begin
q <= d;
end
endmodule
There is a difference in the process of assigning to reg when modeling combinational logic: in this logic we use blocking assignments when modeling sequential logic we use nonblocking ones.
They are of two types. They are big endian and little endian. Memory is separated into two bank, 1:even bank 2:odd bank.
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Prepare at least 3 sets of input data (Test data) along with expected output for testing your program.
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