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Reg data type as Sequential element
module reg_seq_example( clk, reset, d, q);
input clk, reset, d;
output q;
reg q;
wire clk, reset, d;
always @ (posedge clk or posedge reset)
if (reset) begin
q <= 1'b0;
end else begin
q <= d;
end
endmodule
There is a difference in the process of assigning to reg when modeling combinational logic: in this logic we use blocking assignments when modeling sequential logic we use nonblocking ones.
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Discuss scales and sludge
1. Solve the following grouping problem using the DCA method. 2. Use the ROC methodfor the previous problem. 3. Use the MIP method for the problem above assuming a tota
example of branching take place in instructon pipeline
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