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Reg data type as Sequential element
module reg_seq_example( clk, reset, d, q);
input clk, reset, d;
output q;
reg q;
wire clk, reset, d;
always @ (posedge clk or posedge reset)
if (reset) begin
q <= 1'b0;
end else begin
q <= d;
end
endmodule
There is a difference in the process of assigning to reg when modeling combinational logic: in this logic we use blocking assignments when modeling sequential logic we use nonblocking ones.
1's complement representation of decimal number of -17 by using 8 bit representation is ? Ans. (17) 10 = (10001) 2 In 8 bit = 00010001 1's Complement = 11101110
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