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Decoders and multiplexers are termed, medium scale integration (MSI) devices; this term implies that the device is complex in construction and usually its operation as well. Below is shown a block diagram of a 2 -> 4 decoder
The decoder can be thought of as a simple base 10 converter. The binary input's A, B select the base 10 equivalent output, namely O3-> O0. It should be noted that usually the decoder is active low outputs i.e. logic '0' for on and logic '1' for off. Various size decoders are available 2->4, 3->8, 4->16, and 4->10. The operation is made easy by considering the truth table for a 2->4 decoder: -
Within logic we also have sequential logic circuits, the building blocks of these MSI devices are flip flops. There are four basic flip flops namely: SR Flip flop JK Flip flop D-type T-type Note the following truth tables shown below are only valid if the clock is active (usually active low).The operation of these devices are simple in that the devices either stores the last value (i.e. doesn't change), resets, sets, or toggles (i.e. output inverts itself).
It should be noted that the CMOS and TTL logic families have sequential logic within their families and they usually have asynchronous preset (PR) and clear (CL). Let us consider some simple applications of sequential logic.
Three Phase AC Circuit: Alternating circuits thus far discussed have single phase supply system and it's satisfactory for domestic application as light, fan and heating, etc.
A 4000-V, 5000-hp, 60-Hz, 12-pole synchronous motor, with a synchronous reactance of 4 per phase (based on cylindrical-rotor theory), is excited to produce unity power factor at
Explain the Excess three codes - BCD to Decimal Conversion The Excess-3 representation of a number is based on Binary Coded Decimal. It is formed by taking the number in Binary
the p.u. reactance of a 25 MVA, 13.2 kV alternator 0.5 p.u. On a base of 50 MVA and 13.8 KV the p.u. value shall be
To demonstrate a practical method of testing semiconductor diodes.
Q. Show the Enhancement operation of p-channel enhancement mosfet? As the gate terminal is insulated from the channel by the silicon dioxide layer, we can also apply a negative
write an algorithm
Q. For the CS JFET ampli?er circuit of Figure, R D = 2k and R L = 3k. The JFET with ro = 15 k has a voltage gain A v1 =-4.5 when the entire source resistance is bypassed. Fin
Q. Determine the bits required for a D/A converter to detect 1-V change when V ref = 15 V.
what is digital frequency metre?working principle its operation and types application,advantages ,disadvantages
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