Machine coding the programs-microprocessor, Assembly Language

Assignment Help:

Machine Coding the Programs

So far we have describe five programs which were  written  for hand coding  by a programmer. In this, we will now have a deep look at how these programs may be  translate to machine codes. In Appendix, the instruction set along with the Appendix is presented. This Appendix is self-explanatory to hand code mostly of the instructions. The V,S W, D, MOD, REG  and R/M  fields are appropriate decided depending upon the data types, addressing mode and the registers  used. The table shows the details about how to select these fields.

Most of the instructions either have particular opcodes or they may be decided only by setting the V,S, W, D, REG, MOD and R/M fields suitably but the critical point is  the calculation of jump addresses for intra segment branch instructions. Before beginning the coding of call or jump instructions, we will see some simpler coding examples.

Example :

MOV BL, CL

For hand coding this instruction, first we will have to note down the following features.

(i) It sets in the register/memory to/from register format.

(ii) It is an 8-bit operation.

(iii) BL is the destination register and CL is a source register.

Now from the feature (i) by using the Appendix, the op code format is given below.

1485_mcp.jpg

If d =1, then transformation of data is to the register shown by the REG field, for example the destination is a register (REG). If d = 0, the source is a register shown by the REG field. It is an 8-bit operation, therefore w bit is 0. If it had been a 16-bit operation, the w bit would have been 1.From referring to given table to search the REG to REG addressing in it, for example the last column with MOD 11. According to the Appendix when MOD is 11, the R/M field is treated as a REG field. The REG field which is used for source register and the R/M field are used for the destination register, if d is 0. If d =1, the REG field is utilized for destination and the R/M field is used to indicate source. the complete machine code of this instruction comes out to be now.

code    dw       MOD   REG    R/M

MOV BL, CL 1 0 0 0 1 0 0 0     1   1   001    0 1 1= 88 CB


Related Discussions:- Machine coding the programs-microprocessor

Interrupt table-how interrupt table processed-microprocessor, Interrupt Tab...

Interrupt Table Each interrupt level has a booked memory location, called an interrupt vector.  All these vectors (or pointers) are stored in the interrupt table. Table lies at

First generation microprocessor, 1 st Generation Microprocessor : At ...

1 st Generation Microprocessor : At the end of the 70s a group of engineers developed a chip is able to processing data. This chip was called processor chip. Big processors w

Flowchart, ALP to preform of two 16-bit numbers in register addressing mode...

ALP to preform of two 16-bit numbers in register addressing mode

The real time system (rts)-microprocessor, The real time System (RTS) : ...

The real time System (RTS) : Calling the clock real-time is somewhat of a misnomer because it only shows the time setting it has been given. The RTC is the other half of chip

#procedure, #Write a function to calculate the following arithmetic operati...

#Write a function to calculate the following arithmetic operation and return the result. A = 2 + (3x)3 + y/2n (x, y and n are arguments of the function where x is an integer in the

Read architecture:look aside cache-microprocessor, Read Architecture : Look...

Read Architecture : Look Aside Cache In "look aside" cache architecture the main memory is located conflictingthe system interface. Both the cache main memory sees a bus cycle

Interrupt priority management-microprocessor, Interrupt Priority Management...

Interrupt Priority Management The interrupt priority management logic indicated in given figure can be implemented in several ways. It does not required to be present in system

Xor-logical instruction-microprocessor, XOR: Logical Exclusive OR: The XOR...

XOR: Logical Exclusive OR: The XOR operation is again carried out in a similar way to the AND and OR operation. The constraint over operands are also similar. The XOR operation pr

Iret-loop-unconditional branch instruction-microprocessor, IRET : Return f...

IRET : Return from ISR:- When an interrupt service routine is called, before transferring control to it, the IP, CS  register and flag registers are stored in the stack to ment

Hi, i have a question.

i have a question.

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd