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RICS/CISC Architecture
An essential aspect of computer architecture is the design of the instruction set for the processor. The instruction set selected for a specific computer determine the way that machine language programs are constructed. Early computers had simple and small instruction sets, forced basically by the have to minimize the hardware used to implement them. With the advent of integrated circuits as digital hardware became cheaper and computer instructions tend to increase both in complexity and number. Many computers contain instruction sets that include more than hundred and sometimes even more than 200 instructions. These computers also employ a variety of data types and a large number of addressing modes. The trend for computer hardware complexity was influenced by several factors, such as upgrading existing models to provide more customer applications, adding instructions that facilitate the translation from high-level language into machine language programs and striving to develop machines that move functions from implementation of software into hardware . A computer with number of instructions is classified as a Complex Instruction Set Computer and abbreviated CISC.
In the early 1980s, a number of computer designers recommended that computers use fewer instructions with easy constructs so they may be executed much faster within the CPU without having to use memory as frequently. This type of computer is classified as a Reduced Instruction Set Computer or RISC.
Example : Add the contents of the 2000H: 0500H memory location to contents of 3000H: 0600H and store the result in 5000H: 0700H. Solution : Unlike the past example progra
BINARY TO GRAY CONVERSION
RISC Characteristics : The concept of RISC architecture include an attempt to reduce execution time by make simple the instruction set of the computer. The main c
Format of Control Register The format for the control register is given in Figure. Bit 0 of this register might be one before data may be output and bit two might be one
8086 Minimum mode System and Timing In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.All the control si
relocation
External System Bus Architecture : This is a 16 bit processor with 40 pins. It has twenty address pins and out of which sixteen are utilized as data pins. This concept of by us
SCAS : Scan String Byte or String Word:- This instruction scans a string of words or byte for an operand word or byte specified in the register AL or register AX. The string i
INTO : Interrupt on Overflow:- It is executed, when the overflow flag OF is set. The new contents of IP and CS register are taken from the address 0000:0000 as described in INT
Convert 751 to hex and show what it would look like stored at TheNumber WORD ? (hint: answer in hex pairs)
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