Loop level-levels of parallel processing, Computer Engineering

Assignment Help:

Loop Level

At this level, repeated loop iterations are the applicants for parallel execution. However, data dependencies among subsequent iterations may limit parallel execution of instructions at loop level. There is a lot of scale for parallel execution at loop level.

Ex: In the following loop in C language, for (i=0; i <= n; i++)

A(i) = B(i)+ C(i)

Each of the instruction A(i) =B(i)+C(i) can be implemented by different processing elements supplied  there are at least n processing elements. But, the instructions in the loop:

for ( J=0, J<= n, J++) A(J) = A(J-1) + B(J)

Cannot be implemented parallel as A(J) is data dependent on A(J-1).  This means that previous to exploiting the loop level parallelism the data dependencies have to be checked:

 


Related Discussions:- Loop level-levels of parallel processing

What are the entities that swapped out of the main memory, What are the ent...

What are the entities that are swapped out of the main memory while swapping the process out of the main memory? All memory space occupied by the process, process's u-area, and

Illustrate the purchase consummation activity, Illustrate the Purchase Cons...

Illustrate the Purchase Consummation activity? Purchase Consummation: This model lists three activities in the purchase consummation phase: • Receipt of product. • Pl

Explain what the difference between the two readings, The following sentenc...

The following sentences have a (potential) scope ambiguity. Give two translations into predicate logic for each sentence (one formula for each reading), and explain in words what t

Why are interrupt masks provided in any processor, Why are interrupt masks ...

Why are interrupt masks provided in any processor? Interrupt mask enable the higher priority devices comes first and there for lower priority devices comes last. The interrupt

Control hazard and delayed branching, Described Instruction or control haza...

Described Instruction or control hazard? Ans: The pipeline can be stalled due to delay in the availability of an instruction. For instance, this may be a result of a miss in t

Risc approach - computer architecture, RISC Approach - computer architectur...

RISC Approach - computer architecture: The RISC processors only use easy instructions that can be executed within one clock cycle. therefore, the "MULT" command discussed abov

Argument be passed to a subroutine in programming, How many ways can an arg...

How many ways can an argument be passed to a subroutine in programming? Ans)  An argument can be passed in two way in a programming language. They are Pass by Value and Passi

How physical addressing is performed in wan, How physical addressing is per...

How physical addressing is performed in WAN?  WAN networks operate as similar to a LAN. All WAN technology describes the specific frame format a computer uses while sending an

What are the features of the hardwired control, What are the features of th...

What are the features of the hardwired control? A controller that uses this approach can function at high speed. It has little flexibility and the complexity of the instruction

Example of perceptrons, Example of perceptrons: Here as an example fun...

Example of perceptrons: Here as an example function in which the AND boolean function outputs a 1 only but if both inputs are 1 and where the OR function only outputs a 1 then

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd