Draw the circuit diagram for the connections to the EPROM and just one RAM device as defined in the memory map in question 3. You must show all the connections required to operate the memory devices. Clearly identify which ICs are used, label all pins on all parts and label the signals coming to the memory devices.
Draw a bus timing diagram showing the signals: E clock, address lines, data lines, latched address, the chip select for the RAM device and any other significant signals you have used in your circuit. Incorporate delays for decoders, latches and/or bus buffers that match your circuit design. DO NOT use copied or scanned diagrams from study materials. Draw your own timing diagrams.
Calculate the maximum read memory access time available for the RAM device drawn for question 4, using the timing delay values provided on page 420 in the MC68HC912D60A.pdf technical data manual and timing values for 74 series logic parts given in Appendix D. Assume an 8MHz E clock. Show your working.
Identify if the bus timing will function correctly or not. If it will not operate correctly, explain why it does not and how you would modify the design to ensure correct operation.
Draw a circuit diagram showing how you would connect all the lift equipment described above to the built-in I/O ports of the HC12. Do not forget the floor number display. You should select appropriate ports and pins of the HC12 to match the signal types and best achieve the functionality required for all signals. Label all pins on all parts and label the signals used in the circuit.
Remember that all signals into/out of the LCU must be interfaced through a connector, and must provide a 0 Volt (GND) supply reference. Electrical connectors are required so the signals from the devices can connect to the printed circuit board of the LCU. Specific connector types do not need to be specified. You may simply show each connector as a rectangle with numbered pins, clearly showing signal names and a GND reference as required.