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Inhibit Gate
Occasionally it is required to 'hold' one input to an AND gate at a particular logic level in order to disable the entire gate. One method of representing this symbolically is shown in Figure 14, which illustrates a two input gate with an 'INHIBIT' input C carrying an indicator. In this case, with a 1 state at the inhibit input C, the gate is disabled irrespective of the input conditions at A and B. With a 0 state at the inhibit input C however, the gate is now 'enabled' and the output will adopt the 1 state when both input A and input B are at the 1 state.
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