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Q. Illustrate working of Synchronous Counters?
The main drawback of ripple counter is delay in changing the value. How? To understand this let's take a case when state of ripple counter is 0111. Now subsequent state will be 1000 that means change in state of all flip-flops. However will it take place concurrently in ripple counter? No first O0 will change then O1, O2 and finally O3. Delay is proportional to length of the counter. Thus to avoid this drawback of ripple counters we use synchronous counters in which all flip-flops change their states simultaneously. Figure below shows 3-bit synchronous counter.
Figure: Logic diagram of 3-bit synchronous counter
You can understand the working of this counter by analyzing sequence of states (O0, O1, O2) given in Figure below.
Figure: Truth table for 3 bit synchronous counter
The operation can be briefed as: -
i) First flip-flop is complemented in each clock cycle.
ii) Second flip-flop is complemented on occurrence of a clock cycle if current state of first flip-flop is 1.
iii) Third flip-flop is fed by an AND gate which is connected with output of first and second flip-flops. It will be complemented only when first and second flip-flops are in Set State.
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