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Question:
(a) Comment on the general structure of the IAS Computer, illustrate your answer using a diagram.
(b) (i) Define CPU time.
(a) (ii) A program runs in 10 seconds on a computer A, which has a 100 MHZ clock. A designer has to build a machine B that will run the same program in 6 seconds. The designer has determined that a substantial increase in clock rate is possible, but this will affect the rest of the CPU design, causing machine B to require 1.2 times as many clock cycles as machine A for this program. What clock rate should the designer target?
(c) Explain what is meant by a "bus". Name the two types of buses and give a brief description of both.
(d) Explain with the help of a diagram how to accommodate interrupts in an instruction cycle.
1. (e) In respect of computer disks, explain the terms: (i) Sector, (ii) Track, (iii) Cylinder.
What are different EDI components and EDI services? Different EDI components and EDI services are illustrated as: Three main components including services in EDI System are
Write a 'C' program to accept any 3 digit integer number from the keyboard and display the word equivalent representation of the given number
The 2's complement of the number 1101110 is ? Ans. 1's complement of 1101110 is = 0010001 ans hence 2's complement of 1101110 is = 0010001 + 1 = 0010010.
Explain about unix file system architecture
Byteland county is very famous for luminous jewels. Luminous jewels are used in making beautiful necklaces. A necklace consists of various luminous jewels of particular colour. Nec
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In a simple paging system, what information is stored in a typical Look-aside Buffers TLB table entry? A classical TLB table entry contains page# and frame#, while a logical
Q. Example on hamming error correcting code? For illustration a 4-bit matching word can stand for 2 4 =16 values that range from 0 to 15 as: 0000, 0001, 0010, 0011, 0100, 01
a c program to implement multiple stack in a single array
Cache-Only Memory Access Model (COMA) As we have considered earlier, shared memory multiprocessor systems can use cache memories with each processor for decreasing the execution
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