**Q. Illustrate the Execute Cycle?**

The fetch and indirect cycles include a small, fixed sequence of micro-operations. Every one of these cycles has fixed sequence of micro-operations which are common to all instructions.

This isn't true of the execute cycle. For a specific machine with N different opcodes there are N different sequences of micro-operations which can occur. Let's consider some hypothetical instructions:

An add instruction which adds the contents of memory location X to Register R1 with R1 storing the result:

ADD R1, X

Sequence of micro-operations can be:

T1: MAR ← IR (address)

T2: MBR ← [MAR]

T3: R1 ← R1 + MBR

At the beginning of execute cycle IR comprises the ADD instruction and its direct operand address (memory location X). At time T1 address part of the IR is transferred to MAR. At T2 the referenced memory location is read in MBR.

Lastly at T3 contents of R1 and MBR are added by ALU.

Let's discuss one more instruction:

ISZ X it increments content of memory location X by 1. If the result is 0 the subsequent instruction in the sequence is skipped. A possible sequence of micro-operations for this instruction can be:

T1: MAR ← IR (address)

T2: MBR ← [MAR]

T3: MBR ← MBR+ 1

T4: [MAR] ← MBR

If (MBR = 0) then (PC ← PC+ I)

Please remember that for this machine we have presumed that MBR can be incremented by ALU directly.

PC is incremented if MBR comprises 0. This test and action can be applied as one micro-operation. Please note also that this micro-operation may be executedat the time of the same time unit during which updated value in MBR is stored back to memory.

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