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Illustrate the Examples of simulations
- Training (for example pilots, drivers, etc.)
- Running/testing nuclear plants and chemical plants
- trying out equipment to be used in outer space or under sea
- Crash testing cars
- Financial simulations (such as stock market predictions based on various scenarios)
- Population growth (i.e. predict how world's population will increase based on a number of different scenarios)
- Queues (such as simulating queues at supermarket checkouts for example)
- Weather
find the minimum total number of shelves including the loading process
Search mechanisms in Prolog We can utilize this simple Prolog program to describe how Prolog searches: president(X) :- first_name(X, georgedubya), second_name(X, bush). p
Give the example of Spreadsheet By selecting cell C1 and dragging the formula down to C5 the below formulae will be replicated in C2 to C5: (A2*B2), (A3*B3), (A4*B4) and (A5*B5
Explain briefly Dead code Elimination of the commonly used code optimization techniques Dead code Elimination: Code which is unreachable or which does not influence the pr
What is a path name? A pathname is the path from the root by all subdirectories to a specified file. In a two-level directory structure a user name and a file name describe a
Define the component of a process precedence sequence? Ans. Process name, sequence operator and also concurrency operator components are process precedence sequence.
Requirements You are required to program (in a high level language such as C, C++, Java) and implement a cache simulator which will have the following inputs and outputs:-
How many flip flops are required to construct a decade counter ? Ans. 4 FlipFlop's are required because decade counter counts 10 states from 0 to 9 (that is from 0000 to 1001).
How is EISA bus different from ISA bus? Extended Industry Standard Architecture (EISA) is a 32 bit modification to ISA bus. As computers became larger and had wider data buses,
Why a function should have at least one input? There is no strong reason for this in verilog. I think this restriction isn't removed fin SystemVerilog. Some requirements where
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