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Show how a typical DMA controller can be interfaced to an 8086/8085 based maximum mode system.
For 8088 in maximum mode:
The RQ/GT1 and RQ/GT0 pins are utilized to issue DMA signals of request and receive acknowledge. Sequence of events of a usual DMA process
1. Peripheral asserts one of the request pins, for example: RQ/GT1 or RQ/GT0 (has higher priority)
2. 8088 finishes its current bus cycle and enters in a HOLD state
3. 8088 grants the right of bus control through asserting a grant signal via similar pin as the request signal.
4. DMA operation starts
5. Upon end of the DMA operation, there peripheral asserts the request/grant pin again to relinquish bus control.
Typical DMA controller
The inputs to an SRFF are shown in Figure. Determine the value of Q at times t 1 , t 2 , and t 3 .
working principal
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