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How Race Around Condition can be avoided?
Ans:
The race around condition can be avoided if
1. Duration of clock pulse being high is small like comparative to the delay of the gates.
It is difficult due to very small propagation delay in IC's.
2. A master slave JK flip-flop is utilized. In such 2 SR flip-flops there is feedback from the second output to the input of the first flip-flop. + CLK or positive clock pulses are applied to the first clock pulse and clock pulse are inverted at the second flip-flop while second is disabled clk'=0 and clk=1 first flip-flop is enabled.
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1) Short both I/Ps of NAND gate & use the gate as an inverter. 2) Connect any one of the two I/Ps to VCC & use the remaining I/P & use the gate as an inverter.
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