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How many bits must be decoded for chip select? What is the size of decoder when 128 × 8 RAM chips are required to provide a memory capacity of 2048 bytes?Ans. All higher order lines will be applied to decoder input that means that total 128 (27) locations are there and all location can store 8 bits. The no. of inputs to the decoder will be 11 - 7 = 4. And the decoder size will be 4x16. All 16 decoder outputs will be connected to the chip select input of single chips.
Q. What is Enhanced IDE? The principle behind EIDE interface is the same as in IDE interface however this drive has capacities varying from 10.2GB to 20.5GB. The rotation speed
What is referred as memory mapped I/O. The case in computers that employ only set of read and write signals and do not differentiate between memory and I/O address. This is kno
Define main memory and auxiliary memory? The memory unit that communicates directly with the cpu is known as main memory [RAM].Devices that give backup storage are known as aux
Implementation of Arithmetic Circuits for Arithmetic Micro-operation An arithmetic circuit can be implemented by a number of full adder circuits or parallel adder circuits. F
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Q. Illustrate program on hypothetical machine? The program given in figure above is a hypothetical program which performs addition of numbers stored from locations 2001 onwards
What are the differences between SIMULATION and SYNTHESIS Simulation synthesis Simulation is used to verify functionality of the circuit.. a) Functional Simulation:stud
Write short notes on Event Model.
Draw the ISDN address structure and explain how the addressing works? Address Structure: The ISDN address structure is demonstrated in figure. ISDN number part has a maximum
Line A Line is, on a simple level, a mark connecting 2 points. However, how lines are used in an image is extremely important. By varying the quality of line used in an image,
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