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How many bits must be decoded for chip select? What is the size of decoder when 128 × 8 RAM chips are required to provide a memory capacity of 2048 bytes?Ans. All higher order lines will be applied to decoder input that means that total 128 (27) locations are there and all location can store 8 bits. The no. of inputs to the decoder will be 11 - 7 = 4. And the decoder size will be 4x16. All 16 decoder outputs will be connected to the chip select input of single chips.
What is ternary association Associations can be binary, ternary, or have higher order. In use, the vast majority of it is binary or ternary associations. Except a ternary assoc
Discuss in detail the subscriber loop systems. Subscriber Loop System: Every subscriber in a telephone network is linked usually to the nearest switching office by means of w
What are the advantages of electronic payment system? Advantages of the electronic payment system are illustrated below: This gives good security schemes. Four important sec
What is pattern? A pattern is a proven solution to a general problem. Lots of patterns are used. There are patterns for analysis, architecture, design and execution. Patterns c
The Extensible Firmware Interface (EFI) is a specification that defines a software interface among an operating system and platform firmware. EFI is intended as a significantly imp
Q. Explain about disk caching scheme? The disk caching scheme can be used to speed up performance of disk drive system. A set (cache) of buffers is assigned to hold some disk b
One can use the event GET in a report without LDB attribute. False. no one can use the event GET in a report without attribute.
Propositional truth tables: There {X\t} is a substitution that replaces all occurances of variable X with a term representing an object t as: ∀X. A is true if and only
What is phase encoding or Manchestor encoding? It is the method for combining clock information with data. It is a scheme in which alters in magnetization occur for each data
List the factors that determine the storage device performance. i.Access time ii.Cycle time iii.Transfer Rate.
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