Sequential logic gates - sr flip flop, Computer Engineering

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Sequential Logic Gates

SR flip flop

951_SR flip flop.png 1675_SR flip flop3.png

537_SR flip flop1.png 1332_SR flip flop2.png

1) S and R are normally held at 0 so that the outputs remain constant in one of the Q = 601_SR flip flop.png states.

2) A sequence of 0 to 1 to 0 on the S input will ensure that Q = 1 and Q' = 0. (Set action.)

3) A sequence of 0 to 1 to 0 on the R input will ensure that Q = 0 and Q' = 1. (Reset)

4) Circuits are designed so that S = R = 1 never occurs so that Q is always the inverse of Q'. Often the Q' output is labelled 2449_SR flip flop1.png on commercial devices.

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