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Sequential Logic Gates
1) S and R are normally held at 0 so that the outputs remain constant in one of the Q = states.
2) A sequence of 0 to 1 to 0 on the S input will ensure that Q = 1 and Q' = 0. (Set action.)
3) A sequence of 0 to 1 to 0 on the R input will ensure that Q = 0 and Q' = 1. (Reset)
4) Circuits are designed so that S = R = 1 never occurs so that Q is always the inverse of Q'. Often the Q' output is labelledon commercial devices.
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Flag is known as Low order register & Accumulator is known as High order Register.
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