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Explain the Working of Asynchronous (Ripple) Counters?
An external clock is connected to the clock input of the first flip-flop (FF0) only. Thus FF0 changes state at the falling edge of each clock pulse but FF1 changes only when triggered by the falling edge of the Q output of FF0. For the reason that of the inherent propagation delay through a flip-flop the transition of the input clock pulse and a transition of the Q output of FF0 can never occur at exactly the same time. Consequently, the flip-flops cannot be triggered simultaneously producing an asynchronous operation.
A two-bit asynchronous counter
Three-bit asynchronous binary counter
The clock pulse fed in to FF0 is rippled by the other counters after propagation delays, like a ripple on water, hence the name Ripple Counter.The 2-bit ripple counter circuit on top has four different states, every one corresponding to a count value. Likewise, the counter with n flip-flops can have 2 to the power n states. The number of states in a counter is recognized as its mod (modulo) number Therefore a 2-bit counter is a mod-4 counter.
A mod-n counter may as well describe as a divide-by-n counter. This is for the reason that the most significant flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for every n pulses at the clock input of the least significant flip-flop (the one triggers by the clock pulse).
Simulation of a pn Junction An n + p junction is fabricated on a p-type silicon substrate with N A = 8×10 15 cm -3 . The n+ region has a concentration of N D = 1.5×10 18
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