Explain pipeline processing, Computer Networking

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Pipeline Processing

Pipelining is a scheme to realize, overlapped parallelism in the proposed way out of a problem on a digital computer in an economical way. To understand the concept of pipelining, we need to comprehend first the idea of assembly lines in an automated production plant where items are assembled from different parts (phases) and output of one phase/stage becomes the input to other phase. Taking the similarity of assembly lines, pipelining is the method to initiate temporal parallelism in computer operations. Assembly line is the pipeline and the different portions of the assembly line are various phases during which operands of an operation are passed.

To initiate pipelining in a processor P, below steps should be followed:

  • Subdivide the input process into a series of subtasks. These subtasks will create phases of pipeline that are also called segments.
  • Every stage Si of the pipeline according to subtask would execute a number of operations on a different set of operands.
  • When stage Si has finished its operation, results are passed to the subsequent stage Si+1 for next operation.
  • The stage Si receives a new set of input from earlier stage Si-1.

In this manner, parallelism in a pipelined processor is able to be achieved such that m independent operations can be executed concurrently in 'm' segments as displayed in Figure below.

2419_Pipeline Processing.png

Figure: m-Segment Pipeline Processor

The stages or segments are applied as pure combinational circuits executing arithmetic and logic operations over the data streams going through the pipe. Latches are used to divide the stages that are fast registers to hold in-between results between the phases as displayed in Figure below. Each phase Si comprises a latch Li and a processing circuit Ci. The final output is stored in output register R. The flow of data from one phase to other is organized by a common clock. So, in every clock period, one phase transfers its results to other phase.

     2166_Pipeline Processing 1.png

Figure: Pipelined processor


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