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Loop Level
At this stage, following loop iterations are candidates for parallel execution. Though, data dependencies among subsequent iterations can restrict parallel execution of instructions at loop level. There is vast scope for parallel execution at loop level.
Illustration: In the subsequent loop in C language,
For (i=0; i <= n; i++)
A (i) = B (i) + C (i)
Each of the instruction A (i) =B (i) + C (i) may be implemented by different processing elements provided there are at least n processing elements. Though, the instructions in the loop
For (J=0; J<= n; J++)
A (J) = A (J-1) + B (J)
Cannot be executed parallely as A (J) is data dependent on A (J-1). It implies that before using the loop level parallelism the data dependencies should be checked.
Floating gate Avalanche Injection MOS (FAMOS) transistor is used in every cell of EPROM.
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