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Explain in detail about the Dynamic timing
a. Design is simulated in full timing mode.
b. Not all possibilities tested, as it is dependent on input test vectors.
c. Simulations in full timing mode are slow and require a lot of memory.
d. Best method to check asynchronous interfaces or interfaces between different timing domains.
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Which TTL logic gate is used for wired ANDing ? Ans. Open collector output, TTL logic gate is used.
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what are the two memory management scehme(boundary tag system,buddy system)
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