Define setup time and hold time, what will occur when there is setup time and hold tine violation, how to overcome it?

For Synchronous flip-flops, we have particular requirements for the inputs regarding clock signal input there is:

Setup Time: Minimum time Period throughout which data should be stable before the clock makes a valid transition. For example: for a positive edge triggered flip-flop containing a setup time of 2ns so input data must be Stable for 2ns before the clock creates a valid transaction by zero to one

Hold Time: Minimum time period throughout which data should be stable after the clock has made a valid transition. For example: for a posedge triggered flip-flop, along with a hold time of 1ns. Input Data (that is R and S into the case of RS flip-flop) must be stable for at least 1ns after clock has made transition through 0 to 1

Hold time is the amount of time after the clock edge which same input signal has to be held before changing this to make sure that this is sensed appropriately at the clock edge. When there are setup and hold time violations into any flip-flop, this enters a state where its output is unpredictable: that state is termed as metastable state or quasi stable state; at the end of metastable state, then flip-flop settles down to either '1' or '0'. That whole process is termed as metastability.