WAR (write after read) - Data hazards in computer architecture:

WAR (write after read) - j tries to write at destination before it is read by i , hence i  wrongly gets the new value. This cannot happen in our instance pipeline because all reads are near the beginning (in ID) and all writes are late (in WB). This hazard take place when there are some instructions that write results early on in the instruction pipeline, and other instructions that read a source late on in the pipeline.

Because of the normal structure of a pipeline, which naturally reads values before it writes results, such type of hazards are rare. Pipelines for difficult instruction sets that hold up auto increment addressing and need operands to be read lately in the pipeline could build a WAR hazards.

If we customized the DLX pipeline as in the above instance and also read some operands late, such as the source value for a store instruction, a WAR hazard could be take place. Here is the pipeline timing for such type of potential hazard, highlighting    the stage where the     clash    takes place:

If the SW reads R2 at the  time of second half of its MEM2 stage and the Add writes R2 during the first half of its WB stage, the SW will wrongly read and store the value genrated by the ADD instruction.