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Q. Explain about RISC PIPELINING?
Instruction pipelining is frequently used to increase performance. Let's consider this in context of RISC architecture. In case of RISC machines most of the operations are register-to-register. Consequently the instructions can be executed in two stages:
F: Instruction Fetch to get instruction.
E: Instruction Execute on register operands as well as store results in register.
Generally the memory access in RISC is performed by STORE and LOAD operations. For these instructions subsequent steps may be required:
F: Instruction Fetch to get instruction
E: Effective address calculation for desired memory operand
D: Register to memory or Memory to register data transfer by bus.
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