Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Q. Explain about Associative Memory Organisations?
The associative memory is arranged in w words with b bits per word. In w x b array, every bit is known as a cell. Every cell is made up of a flip-flop which comprises some comparison logic gates for read-write operations and pattern match. So it is possible to write or read concurrently because of this logic structure. A set of bit cells of all the words at the same place in vertical column is termed as bit slice as displayed in Figure below.
Figure: Associative memory
In organisation of an associative memory subsequent registers are used:
• Comparand Register (C): This register is used to hold operands that are being searched for or being compared with.
• Masking Register (M): It might be possible all bit slices are not involved in parallel operations. Masking register is used to disable or enable bit slices.
• Temporary (T) and Indicator (I) Registers: Indicator register is used to hold the current match patterns and temporary registers are used to hold the prior match patterns.
What is Delegation? A delegate acts like a strongly type function pointer. Delegates can raise the methods that they reference without making explicit calls to those methods. D
Define cache line. Cache block is used to refer to a set of contiguous address location of some size. Cache block is also referred to as cache line.
Q. Example of processor arrangements? !HPF$ PROCESSORS P (10) This initiates a group of 10 abstract processors assigning them combined name P. !HPF$ PROCESSORS Q (4, 4)
Parent class of all Java classes is? All Java class's parent class is java. lang.object.
Page fault frequency in an operating system is reduced when the? When locality of reference is appropriate to the process so Page fault frequency in an operating system is redu
what is time out based schemes in concurrency control
design a dfa which accept all the string over a and b ending with ab or ba
Basic idea: However in the above decision of tree which it is significant that there the "parents visiting" node came on the top of the tree. Whether we don't know exactly the
The illustration of the mouse on-screen. Depending on your settings, the cursor can be many dissimilar things.
Q. Feature of micro-instruction execution? Feature of micro-instruction execution is micro-instruction sequencing which involves address calculation of next micro-instruction.
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd