Give the circuit of a TTL NAND gate and explain its operation in brief.

Ans:

Operation of TTL NAND Gate: Fig.(d) Demonstrates a TTL NAND gate with a totem pole output.   The    totem pole output implies that transistor T₄ sits atop T₃ in order to give low output impedance.  The low output impedance means a short time constant RC therefore the output can change rapidly from one state to the other. T₁ is a multiple type emitter transistor. Such transistor can be thought of like a combination of various transistors along with a common collector and base. Multiple emitter transistors along with about 60 emitters have been developed. In this figure, T₁ has 3 emitters thus there can be three inputs A, B, C. The transistor T₂ functions as a phase splitter since the emitter voltage is out of phase along with the collector voltage. The transistors T₃ and T₄ by the totem pole output, the capacitance CL shows the stray capacitance and so on. The diode D is added to make sure that T₄ is cut off while output is low. The voltage drop of diode D remains the base-emitter junction of T₄ reverse biased therefore only T₃ conducts while output is low. The operation can be described briefly by three conditions as specified below:

Condition 1: At least one input is low (that is, 0).  Transistor T₁ saturates. Thus, the base voltage of T₂ is almost zero. T₂ is cut off and forces T₃ to cut off.  T₄ functions as an emitter follower and couples a high voltage to load. Output is high (that is Y=1).

Condition 2: Each input is high. The emitter base junctions of T₁ are reverse biased. The collector base junction of T₁ is forward biased. Therefore, T₁ is in reverse active mode. The collector current of T₁ flows in reverse direction. Because this current is flowing in the base of T₂, the transistors T₂ and T₃ saturate and then output Y is low.

Condition 3: The circuit is operating under II while one of the inputs becomes low. The consequent emitter base junction of T₁ starts conducting and T₁ base voltage drops to a low value.  Thus, T₁ is in forward active mode. The high collector current of T₁ shifts the stored charge in T₂ and T₃ and hence, T₂ and T₃ go to cut-off and T₁ saturates and then output Y returns to high.

Fig.(d) Logic Diagram of TTL NAND Gate with Totem Pole Output