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Instruction buffers
For taking the complete advantage of pipelining pipelines must be filled continuously. So instruction fetch rate must be matched with pipeline consumption rate. To accomplish this instruction buffers are used. Instruction buffers in CPU have high speed memory for accumulating the instructions. The instructions are prefetched in buffer from main memory. Alternative for the instruction buffer is cache memory between main memory and CPU. The benefit of cache memory is it can be used for both data and instruction however cache needs more complicated control logic than instruction buffer. Some pipelined computers have implemented both.
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