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Q. Draw the logic diagram of an SR latch using only NAND gates, and obtain the truth table for that implementation.
A 3-phase transmission line is 200km long. The line has a per phase series impedance of 0.25+j0.45 Ω/km and shunt admittance of j7.2 μS/km. The line delivers 250MVA, at 0.6 lagging
Q. Find the frequency of oscillation, amplifier gain ? The transfer function is found to be where the equation is written as a Laplace transform (s=jw). Analysis of thi
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Why is the signal first attenuated and then amplified?
Explain cache structure in Pentium. Cache structure in Pentium: The cache in the Pentium has been changed by the one determined in the 80486 microprocessor. The Pentium has t
what is emitter efficiency
Advantages of High level Languages a.It is easy to learn write and debug the program written in high level languages. b.Programs are more legible as compared to m
Q. Counters are used to realize various dividers in the schematic representation of the digital clock shown in Figure. The blocks labeled "logic array" are logic gate combinations
Derive the mathematical 3-D heat conduction equation in Spherical Coordinates? A furnace is made up of three layers of thicknesses 250 mm, 150 mm nad 100 mm with thermal conduct
A 10 - hp, 250-V shunt motor has an armature circuit resistance of 0.5 and a ?eld resistance of 200 . At no load, rated voltage, and 1200 r/min, the armature current is 3 A. At
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