What are disadvantages of the asynchronous reset and synchronous reset?

Disadvantages of asynchronous reset:

Make sure that the release of the reset can arise within one clock period. When the release of the reset occurred onto or near a clock edge, in that case the flip-flops went metastable.

Disadvantages of synchronous reset:

Problem along with synchronous resets is which the synthesis tool cannot easily differentiate the reset signal from any other data signal. Synchronous resets may require a pulse stretcher to guarantee a reset pulse width extensive enough to make sure reset is present throughout an active edge of the clock. When you have a gated clock to save power, in that case the clock may be disabled coincident along with the assertion of reset. Simply an asynchronous reset will act in this situation, when the reset might be removed prior to the resumption of the clock. Designs which are pushing the restrictive for data path timing, cannot give to have added gates and additional net delays into the data path because of logic inserted to handle synchronous resets.