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Differentiate between pre-emptive and non-pre-emptive scheduling.Pre-emptive scheduling: in its approach, center processing unit can be taken away from a process if there is a require while in a non-pre-emptive approach if one time a process has been specified the CPU, the CPU can't be taken away from such process, unless the process leaves or completes the CPU for performing an Input and Output.Pre-emptive scheduling is more helpful in high priority process that requires immediate response, for illustration in real time system. Whereas in non-preemptive systems, jobs are made to wait through longer jobs, but treatment of each process is fairer.
What are the Types of Assemblies? One of the drawback of using Visual Studio.NET and the .NET framework to develop applications has been the lack of cross-platform support. As
Define register file. All general purpose registers are combined into a one block called the register file.
Problem: (i) What are the main threats that an organisation holding sensitive data, such as Public Data, on computer storage must guard against? (ii) To protect such data,
RISC architecture - computer architecture: What is reduced regarding it? The answer of this question is that to make all instructions the equal length the number of bits that
what is cursor
Q. When an object travels with constant velocity does its average velocity during any time interval differ from its instantaneous velocity at any instant? Answer:- No It i
Quadratic probing: In the above case when the first insertion is made the probability of latest element being inserted in a certain position is 1/n where n is the size of the a
Common channel signalling ? Common channel signalling requires no additional transmission help or facilities.
RAW and WAW - Data hazards: RAW (read after write) - j tries to read a source before i writes it, hence j wrongly gets the old value .This is the most usual type of
Q. Concurrently read concurrently write? It is one of the models derived from PRAM. In this model the processors access the memory locations simultaneously for reading and writ
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