Difference between blocking and non-blocking

Verilog  language  has  two  forms  of  the  procedural  assignment  statement:  blocking  and  nonblocking. The two are distinguished by = and <= assignment operators. Blocking assignment statement (= operator) acts much like in traditional programming languages. Whole statement is done before control passes on to the next statement. Non-blocking (<= operator) evaluates all the right-hand sides for current time unit and assigns left-hand sides at the end of the time unit.

For example, the following Verilog program

// testing blocking and non-blocking assignment

module blocking;

reg [0:7] A, B;

initial begin: init1

A = 3;

#1 A = A + 1; // blocking procedural assignment

B = A + 1;

$display("Blocking: A= %b B= %b", A, B );

A = 3;

#1 A <= A + 1; // non-blocking procedural assignment

B <= A + 1;

#1 $display("Non-blocking: A= %b B= %b", A, B );

end

endmodule

produces the following output:

Blocking: A= 00000100 B= 00000101

Non-blocking: A= 00000100 B= 00000100

The  effect  is  for  all  non-blocking  assignments  to  use  old  values  of  variables  at  the beginning of current time unit and to assign registers new values at the end of the current time unit.  This  reflects  how  register  transfers  take place in  some  hardware  systems.  Blocking  procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential.