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All components of computer communicate with processor by the system bus. Which means I/O devices required to be attached to system bus. But I/O devices aren't connected directly to computer's system bus. In its place they are attached to an intermediate electronic device interface known as a device controller that in turn is attached to system bus. Therefore a device controller is an interface between a system bus and an I/O device. On one side it knows how to communicate with I/O device associated to it and on the other it knows how to communicate with computer's CPU or processor and memory via the system bus.
In 32bit IP Addressing scheme all 1's represent? All 1's represent limited broadcast in 32 bit IP Addressing scheme.
Q. Explain the graphic display system? The function of your graphic display system is to display bit-mapped graphics on your monitor. The image displayed on your system so com
I want to know basic about it
A class that has no functionality of its own is an Adaptor class in C++. Its member functions hide the use of a third party software component or an object with the non-compatible
What are the registers generally contained in the processor? MAR-memory address register MDR-memory data register IR-Instruction Register RO-Rn-General purpose registe
They are of two types. They are big endian and little endian. Memory is separated into two bank, 1:even bank 2:odd bank.
What does the swapping system do if it identifies the illegal page for swapping? If the disk block descriptor does not have any record of the faulted page, then this causes the
Hardware interrupts: Hardware interrupts -from I/O devices, processor, memory Software interrupts-produced by a program. Direct Memory Access (DMA) Interrupt or Poll
Q. Basic Tradeoff of concerns for instruction set design? Basic Tradeoff: Smaller instruction (less space) vs. desire for more powerful instruction repertoire. Generally p
Why a task can n ot return a value? If tasks can return values then Let's take a look at the below example. A=f1(B)+f2(C); and f1 and f2 had delays of say 5 and 10? Whe
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