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Define a Gate Fix ASIC-based design in short.
Gate Fix ASIC-based design:
A Gate Fix implies that a select number of gates and their interconnections may be subtracted or added through the design (for example the netlist). This ignores resynthesis. Gate fixes preserve the earlier synthesis effort and involve manually adding gates, editing a gate-level netlist and removing gates, so on. Gate level fixes influence all type layers of the chip and masks.
Step 1: Click on Edit Step 2: Select reference Step 3: Select Translation Step 4: Click on SSI Step 5: For showing the SSI file; choose one of the following options:
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