Counter-controlled analog to digital converter, Electrical Engineering

Assignment Help:

Q. Counter-controlled analog to digital converter?

Figure shows the block diagram of a counter-controlledA/Dconverter. Resetting the binary counter to zero produces D/A output voltage V2 = 0 and initiates the analog-to-digital conversion. When the analog input V1 is larger than the DAC (D/A converter) output voltage, the comparator output will be high, thereby enabling the AND gate and incrementing the counter. V2 is increased

1526_Counter-controlled analog to digital converter.png

as the counter gets incremented; when V2 is slightly greater than the analog input signal, the comparator signal becomes low, thereby causing the AND gate to stop the counter. The counter output at this point becomes the digital representation of the analog input signal. The relatively long conversion time needed to encode the analog input signal is the major disadvantage of this method.


Related Discussions:- Counter-controlled analog to digital converter

FLOW CHART TO RUN MOTOR, IFYOU AVE TWO DC MOTOR,RELAY,TWO BATTERYAND MICROC...

IFYOU AVE TWO DC MOTOR,RELAY,TWO BATTERYAND MICROCONTROLLER FLOW CHART TO RUN MOTOR AND CONTROL TWO BATTERIES

Obtain an expression for b, Q. Consider an infinitely long, straight wire (...

Q. Consider an infinitely long, straight wire (in free space) situated along the z-axis and carrying current of I A in the positive z-direction. Obtain an expression for ¯B everywh

Evaluate maximum directive gain, Q. For a pyramidal-horn antenna, the maxim...

Q. For a pyramidal-horn antenna, the maximum directive gain is given by occurring when the aperture dimensions are A ∼ = √3λLandB = 0.81A. The principal-plane beam- widths

Rectifier, wave form of half wave rectifier with rl load

wave form of half wave rectifier with rl load

Induced emf, applications of dynamically induced emf

applications of dynamically induced emf

How address and data lines are demultiplexed in 8085, How address and data ...

How address and data lines are demultiplexed in 8085? AD0-AD7 lines are multiplexed and the lower half of address A0-A7 is available only during T1  of the machine cycle. This

What is synchronous data transfer, What is synchronous data transfer? I...

What is synchronous data transfer? It is a data method which is used when the I/O device and the microprocessor match in speed. To transfer a data to or from the device, the us

#title.Shockley diode, I want proof of shockley diode equation with all ste...

I want proof of shockley diode equation with all steps

How a transistor in common-base configuration amplify signal, Q. With a cir...

Q. With a circuit diagram explain how a transistor in common-base configuration amplify signals.  The common-base terminology is derived from the fact that the base is common t

For zero flag - return instructions, For zero flag  RZ ( Return on Z...

For zero flag  RZ ( Return on Zero) and RNZ ( Return on no zero) Instructions RZ  returns from the subroutine to the  calling  program, if zero flag  is set  (Z= 1). The

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd