Counter-controlled analog to digital converter, Electrical Engineering

Assignment Help:

Q. Counter-controlled analog to digital converter?

Figure shows the block diagram of a counter-controlledA/Dconverter. Resetting the binary counter to zero produces D/A output voltage V2 = 0 and initiates the analog-to-digital conversion. When the analog input V1 is larger than the DAC (D/A converter) output voltage, the comparator output will be high, thereby enabling the AND gate and incrementing the counter. V2 is increased

1526_Counter-controlled analog to digital converter.png

as the counter gets incremented; when V2 is slightly greater than the analog input signal, the comparator signal becomes low, thereby causing the AND gate to stop the counter. The counter output at this point becomes the digital representation of the analog input signal. The relatively long conversion time needed to encode the analog input signal is the major disadvantage of this method.


Related Discussions:- Counter-controlled analog to digital converter

Explain the conductyvity of atom with four valence electrons, Atoms with fo...

Atoms with four valence electrons are good conductors. This statement is true or false. Ans:  Atoms are good conductors with four valence electrons. This statement is false.

What is own-exchange routing, Q. What is Own-exchange routing? Distribu...

Q. What is Own-exchange routing? Distributed routing or own-exchange routing enables alternative routes to be chosen at intermediate nodes. Hence the strategy is capable of res

Bipolar junction transistor, Bipolar junction transistor: Transistors ...

Bipolar junction transistor: Transistors are so named as they conduct via using both majority and minority carriers. The bipolar junction transistor that is abbreviated as BJT

D flip-flop - latch or delay element, Q. D flip-flop - latch or delay eleme...

Q. D flip-flop - latch or delay element? The symbol for the clocked D flip-flop is shown in Figure (a), in which the two output terminals Q and ¯ Q behave just as in the SRFF,

Mov instruction, MOV Instruction Op code  format  of MOV  instruction i...

MOV Instruction Op code  format  of MOV  instruction is as follows : Replace the  codes of destination register and source  register with code of  required  register from.

Superposition theorem, how do you work it out if there are 3 sources in par...

how do you work it out if there are 3 sources in parallel?

Commercial losses in electrical systems, Commercial Losses in Electrical Sy...

Commercial Losses in Electrical Systems Commercial losses are caused by pilferage, theft, defective meters, and errors in meter reading and in estimating un-metered supply of

#title.ec 1., draw the gain frequency response of an RC coupled circuit? di...

draw the gain frequency response of an RC coupled circuit? discuss fall in gain at very low and very high frequencies?

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd