Counter-controlled analog to digital converter, Electrical Engineering

Assignment Help:

Q. Counter-controlled analog to digital converter?

Figure shows the block diagram of a counter-controlledA/Dconverter. Resetting the binary counter to zero produces D/A output voltage V2 = 0 and initiates the analog-to-digital conversion. When the analog input V1 is larger than the DAC (D/A converter) output voltage, the comparator output will be high, thereby enabling the AND gate and incrementing the counter. V2 is increased

1526_Counter-controlled analog to digital converter.png

as the counter gets incremented; when V2 is slightly greater than the analog input signal, the comparator signal becomes low, thereby causing the AND gate to stop the counter. The counter output at this point becomes the digital representation of the analog input signal. The relatively long conversion time needed to encode the analog input signal is the major disadvantage of this method.


Related Discussions:- Counter-controlled analog to digital converter

What is memory mapping, What is memory mapping? The assignment of memor...

What is memory mapping? The assignment of memory addresses to several registers in a memory chip is known as memory mapping.

Convert these numbers to their decimal values, Q. Consider the three BCD nu...

Q. Consider the three BCD numbers listed below. 0001 1000 0101 1000 0010 0001 0011 1000 0100 0011 0101 0101 a) Convert these numbers to their decimal values. b) Conv

Explain common base configuration, Q. Explain common base configuration? ...

Q. Explain common base configuration? Common-base transistor amplifiers are so-called because the input and output voltage points share the base lead of the transistor in commo

Explain a miller sweep generator, Q. With the help of circuit diagram expla...

Q. With the help of circuit diagram explain a Miller Sweep generator Figure given below shows the circuit of a Miller integrator or a sweep circuit. Transistor Q1 acts as a swi

Explain this phenomenon, (a) Design a 2 nd  order Sallen and Key low pass ...

(a) Design a 2 nd  order Sallen and Key low pass active filter with the following characteristics: Nominal Cut-off Frequency: 1.6 kHz Variable Gain: 0 to 7.5 dB You may a

Logically and the contents of memory, Logically AND the contents of memory ...

Logically AND the contents of memory Contents of memory  location,  whose address is specified by HL register pair are logically AND with the  contents  of the accumulator. The

Biasing clamper, Ask question #Minwhat is biasing of clamper imum 100 words...

Ask question #Minwhat is biasing of clamper imum 100 words accepted#

What do you mean by sub address, Q. What do you mean by sub address? A ...

Q. What do you mean by sub address? A sub address, though a part of the ISDN address, isn't considered as an integral part of the numbering scheme. Sub address is carried in a

Banking system , banking system is the collection of financial entities, in...

banking system is the collection of financial entities, infrastructure and practices which support financial transactions . system tech is a software system to handle their transa

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd