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Q. Counter-controlled analog to digital converter?
Figure shows the block diagram of a counter-controlledA/Dconverter. Resetting the binary counter to zero produces D/A output voltage V2 = 0 and initiates the analog-to-digital conversion. When the analog input V1 is larger than the DAC (D/A converter) output voltage, the comparator output will be high, thereby enabling the AND gate and incrementing the counter. V2 is increased
as the counter gets incremented; when V2 is slightly greater than the analog input signal, the comparator signal becomes low, thereby causing the AND gate to stop the counter. The counter output at this point becomes the digital representation of the analog input signal. The relatively long conversion time needed to encode the analog input signal is the major disadvantage of this method.
Q. For a pyramidal-horn antenna, the maximum directive gain is given by occurring when the aperture dimensions are A ∼ = √3λLandB = 0.81A. The principal-plane beam- widths
Simplify using k-map f(A,B,C,D)=?M(4,6,10,12,13,15) Using behavioral modeling in xilinx VHDL
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