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Described Instruction or control hazard?
Ans: The pipeline can be stalled due to delay in the availability of an instruction. For instance, this may be a result of a miss in the cache, needing the instruction to be fetched from the primary memory. Such hazards are frequently called control hazards or instruction hazard.
Explained delayed branching?
Ans: Delayed branching which is used to minimize the penalty incurred as a result of conditional branch instruction. The following location of the branch instruction is known as delay slot. The instructions in the delay slots are always fetched and they are set such that they are fully executed whether branch is taken or not. That is branching takes place 1 instruction afterwards than where the branch instruction seem in the instruction sequence in the memory therefore the name delayed branching.
pipelining hazards
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